This invention relates to phase-locked loops (PLL's), and more particularly to phase pre-alignment of clocks to the phase detector of the PLL.
Integrated circuit (IC) performance is often limited by clock generation and distribution. High-frequency synchronous systems are sensitive to clock skew. Clock skew is the phase difference between an input clock and an output clock. Clock skew should be minimized to prevent race conditions, to shorten setup time and hold time requirements, and to increase the maximum possible operating speed.
CMOS technology scaling has produced a requirement for low supply voltages to maintain device reliability with the smaller, more easily damaged devices. Employing a low supply voltage minimizes power consumption in digital circuits and extends battery life. However, it is quite challenging to design analog circuits at a supply voltage as low as 1V using conventional approaches, especially for high frequency clock generation.
Currently, clock generation is commonly based on three techniques including Delay-Locked Loops (DLLs), Synchronous Mirror Delays (SMDs) and Phase-Locked Loops (PLLs). In most cases, DLLs and SMDs provide only a fixed frequency, while PLLs can provide multiple output frequencies, which can be even higher than the input frequency.
DLLs and SMDs are composed of delay chains to perform phase adjustment and alignment. However, speed is inherently limited by the delay of individual cells and thus by the voltage supply and the process parameters. This frequency limitation can be overcome by using an LC oscillator as the core in a PLL.
FIG. 1 shows a prior-art PLL. The high-frequency output signal VCOUT of an LC voltage-controlled oscillator VCO 41 is divided down by feedback divider 58 to a lower feedback frequency. The output signal of divider 58 is applied to one of the inputs of phase-frequency detector 54 to perform phase and frequency comparison with the divided-down input clock as a reference clock applied to the other input. The reference clock REFCLK is divided by M by input divider 52.
Phase-frequency detector 54 controls charge pumps 56 to sink or source currents to loop filter 57, which increases or decreases the output voltage of loop filter 57. Loop filter 57 is used to filter out high-frequency noise from charge pumps 56 and to stabilize the closed-loop system of PLL 10.
The output voltage of loop filter 57 is applied as the control voltage to VCO 41 to control its output frequency. This negative feedback system can ensure that the output frequency of the oscillator equals the input clock frequency multiplied by dividing ratio N/M in the locked condition. The phase difference between the VCO output and input clock are not necessary zero due to the intrinsic delay in dividers 52, 58 and the mismatch due to the complementary outputs of phase-frequency detector 54 and current mismatch in the charge pumps 56.
What is desired is a better-aligned PLL. A PLL with lower internal skew is desirable. A high-frequency PLL that can operate with low supply voltages is desired.